This invention relates to a latching circuit which is described more particularly as a clocked latching circuit.
In the prior art, a digital latching circuit includes input and latching pairs of emitter-coupled transistors. The input and latching pairs of transistors are responsive to states of input signals representing data bits for producing output signals having the binary value of the input signals but controlled by a clock cycle. Pulses of current are applied alternately to the common emitter circuits of the input and output pairs for alternately quantizing the state of the input signal and latching that quantized state.
There are several problems with the prior art latching circuit. When more latches than one are cascaded, level shifting is required between those latches. Such level shifting circuitry reduces speed of operation and increases propagation delay. The prior art latching circuit also is slowed because it is biased near saturation. Additionally the prior art latching circuit is highly sensitive to supply voltage level.